At the Supercomputing Conference (SC13), Intel revealed that future processors coming out of its fabs will house more features. This includes memory chips, stacked memory dies, integrated high-speed switches and optical fabrics. The improvements are part of Intel’s roadmap for customizing its high-end processors such as the Xeon and Xeon Phi chips.
Intel will be working with its technical computing customers to provide these highly integrated processors. This collaboration will result in the customiziation of Intel’s in-package memory architectures to match the specific needs of each customer’s. The addition of memory management units will allow customers the choice of implementing caches, flat memory spaces or hybrid combinations of these.
“We have the transistor budget to do customized innovation, and secondly we have a design methodology for system-on-chip and an architectural modularity that allows us the ability to work with our customers to customize products at various levels. We are moving forward into workload-optimized architectures at a level of collaboration with our customers that we hadn’t done previously.” – Rajeeb Hazra, Intel VP of the technical computing group
Knights Landing (code name for the next-gen Xeon Phi) is first in line to receive these modifications, the chip includes in-package memory dies alongside the processor. Other features `included on Knights Landing are math coprocessors, I/O controllers and memory controllers.
“We are looking at various new classes of integrations, from integrating portions of the interconnect as well as next-generation storage and memory much more intimately onto the processor die,” – Hazra.
